Flash memory has been widely used as a memory using threshold changes of MOS (Metal Oxide Semiconductor) FETs due to the charge amount of the floating gate that is the memory-functional film. Among 1-transistor type memories of the flash memory are NOR type, DINOR type, NAND type, AND type, and the like. Among them, the AND type has a characteristic that it can be made smaller in cell area and still equivalent in read speed, compared with the NOR type. Further, the AND type is enabled to perform erase operations on the word line basis, thus having a characteristic that it is smaller in erase unit than the NAND type.
However, in the above-described conventional AND type memory, the cell area is about 8F2 (where F is a minimum machining pitch), larger than 6F2 of the NAND type memory, which has been an obstacle to higher integration as a problem.
A detailed explanation is given below. FIG. 32 shows a planar pattern layout in the conventional AND type memory cell array. Referring to FIG. 32, in the conventional AND type cell array, a plurality of device isolation regions 1 for partitioning the semiconductor substrate are formed so as to extend straight in one direction (lateral direction in FIG. 32). The pitch of the device isolation regions 1 along the longitudinal direction is set to 4F. Between one pair of device isolation regions 1, 1, a source line 2 and a bit line 3 each composed of a dopant diffusion layer in the semiconductor substrate are formed so as to extend straight in the lateral direction and to be spaced from each other by a distance of 1F. On the other hand, in the vertical direction (longitudinal direction in FIG. 32) against the lateral direction, a plurality of word lines 4 composed of polycrystalline silicon are formed so as to extend straight at a pitch of 2F in the lateral direction. Then, a region interposed between the source line 2 and the bit line 3 and covered with a word line 4 becomes a channel region 5. One memory cell is a region represented by a longitudinally 4F and laterally 2F sized rectangular shape 6 depicted by two-dot chain line in FIG. 32, the area thereof being 8F2 (=4F×2F) larger than that of the NAND type memory, 6F2.
As shown above, the AND type memory, although having such characteristics as the read speed equivalent to that of the NOR type and the capability of word-line basis erase operation, which is smaller than in the NAND type, yet has the problems of larger area and incapability of higher integration as compared with the NAND type.